Recently, an increase in operation speed of semiconductor storage has been desired with that of CPU. For example, synchronous-type semiconductor storages that operate synchronizing with an external clock exceeding 100 MHz have been proposed in Japanese patent application laid-open Nos. 61-148692 (1986), 6-76566 (1994) and 7-45068 (1995) etc.
A typical conventional semiconductor storage is, as shown in FIG. 1, composed of an input receiver 1 that an external clock CLK is input, an input receiver 2 that a /CS signal (chip selection signal) is input, an input receiver 3 that a /RAS signal (row address strobe signal) is input, an input receiver 4 that a /CAS signal (column address strobe signal) is input, an input receiver that a /WE signal (write enable signal) is input, an input receiver 6 that an address signal ADD is input, an input receiver 7 that a data input signal is input, a pulse generating circuit 8 that the output of the input receiver 1 is input, an inverter I15 that the output of the pulse generating circuit 8 is input and outputs an internal synchronous signal ICLK, a command decoder 10 that the outputs of the input receivers 2, 3, 4, 5 and 6 and the internal synchronous signal ICLK are input and outputs several decoded control signals 12, and an internal circuit 11 that the control signal 12 and the outputs of the input receivers 6 and 7 are input and outputs data to a data output terminal.
Also, the pulse generating circuit 8 is, for example, composed of an inverter I1 that receives an input to the pulse generating circuit 8, an inverter I2 that the output of the inverter I1 is input, an inverter I3 that the output of the inverter I2 is input, and a NAND gate NA1 that the input to the pulse generating circuit 8 and the output of the inverter I3 are input.
FIG. 2 is an illustration of operation waveforms showing the relation between the external clock CLK and the internal synchronous signal ICLK. When the external clock CLK shifts from Low level to High level and then the output of the input receiver 1 shifts to High level as well, the output of the NAND gate NA1 becomes Low because the output of the inverter I3 was High at that time. Thereby, the internal synchronous signal ICLK, i.e., the output of the inverter I15, becomes High. With the shifting of the output of the input receiver 1 to High level, the output of the inverter I3 becomes Low after a certain time. Thereby, the output of the NAND gate NA1 becomes High and the output of the inverter I15, the internal synchronous signal ICLK, becomes Low.
Thus, the internal synchronous signal ICLK is produced by the shifting of the external clock CLK from Low level to High level.
Synchronizing with the internal synchronous signal ICLK, the levels of the external signals /CS, /RAS, /CAS and /WE are taken into the command decoder 10. Then, the control signals 12 are produced by latching and decoding them.
An example of a use of the conventional synchronous-type semiconductor storage will be explained in FIG. 3. As shown, at a timing C1 when the external clock CLK shifts from Low level to High level, an active command is input with setting /CS, /RAS, /CAS and /WE to be Low, Low, High and High levels, respectively. Simultaneously, a row address (ROW) is given as an address signal ADD. After a certain time, at a timing C2 when the external clock CLK shifts from Low level to High level, a read command is input with setting /CS, /RAS, /CAS and /WE to be Low, High, Low and High levels, respectively. Simultaneously, a column address (COL) is given as an address signal ADD. Then, data according to the row address and column address input are output to the data output terminal. Further, after a certain time, at a timing C3 when the external clock CLK shifts from Low level to High level, a precharge command is input with setting /CS, /RAS, /CAS and /WE to be Low, Low, High and Low levels, respectively. Thereby, the internal circuit is set in a stand-by state to allow the next access.
On the other hand, an example of a use of an asynchronous-type dynamic RAM, which similarly relates to reading out of data, will be explained in FIG. 4. As shown, at a timing C1, shifting /RAS from High to Low, an active command is input and a row address (ROW) is simultaneously given as an address signal. After a certain time, at a timing C2, while keeping /WE High level and shifting /CAS from High to Low, a read command is input and a column address (COL) is simultaneously given as an address signal. Then, data according to the row address and column address input are output to the data output terminal. Further, after a certain time, at a timing C3, a precharge command is input by returning /RAS and /CAS to High level. Thereby, the internal circuit is set in a stand-by state to allow the next access.
In comparing the example of the synchronous-type semiconductor storage in FIG. 3 with the example of the asynchronous-type semiconductor storage in FIG. 4, a time (t1) from the timing C1 until outputting data DOUT to the data output terminal is about equal to each other. Also, a time (t2) from the timing C1 until inputting the precharge command and further a time (t3) from the timing C1 until again inputting the active command after conducting the precharge are equal to each other. However, as to the operating frequency of external signal, the asynchronous-type semiconductor storage in FIG. 4 has only an external signal to be operated at a frequency of (1/2t3)Hz at the maximum whereas the synchronous-type semiconductor storage in FIG. 3 has an external clock CLK to be operated at a frequency of (3/t3)Hz at the maximum.
In the conventional synchronous-type semiconductor storage, to output one-bit data needs 3 cycles of operations of the external clock CLK. Therefore, to reduce t3 to conduct a memory cell test in a short time, a memory tester to operate at a high frequency is necessary.
For example, to conduct the test at t3=100 ns, the external clock has to be operated at 33 MHz. Particularly in a test process to contact a wafer with a probe, a test environment to operate at 33 MHz must be arranged taking the impedance, load etc. of the probe into account. In such a case, a further investment will be required, compared with the test environment of the asynchronous-type semiconductor storage.
Also, in a burn-in test that is generally conducted in a test after fabrication, a number of semiconductor storages are tested in parallel. Therefore, the tester can only drive a low-frequency signal because it has to drive a high load. Because of this, in testing the conventional synchronous-type semiconductor storage by the tester, an access time to one-bit memory cell becomes longer than that in the asynchronous-type semiconductor storage. Thus, the test time must be significantly prolonged.